1. Field of the Invention
The present invention relates to a semiconductor memory device and a test method thereof, and particularly relates to a semiconductor memory device capable of checking whether a one-to-one correspondence is established between blocks and addresses in access operation.
2. Description of the Related Art
In a semiconductor memory device, in some cases, a wiring short occurs owing to dust generated during manufacturing or the like, which causes a defect (multi-selection defect) in which blocks (or rows) in a memory cell array are simultaneously selected at the time of access and a defect in which a one-to-one correspondence is not established between addresses and blocks (See FIG. 17 and FIG. 18).
Accordingly, in a test process, such a defective block needs to be replaced with a redundant block. Alternatively, they are treated as defective blocks in a test process, and when the number of defective blocks exceeds a permissible value of a chip, the defective chip needs to be removed.
FIG. 19 shows a test process of detecting such a defective block. As shown in FIG. 19, when the test process is started, “0” is written into all blocks (step S10). Namely, all memory cells in all the blocks are changed from “1” to “0”.
Then, a block address N which is a variable is reset to “0” (step S12). Subsequently, a block erase is performed in a block at the block address N=0 (step S14). Namely, all data in memory cells in the block is erased, and the memory cells therein are changed to “1”.
Thereafter, data is read from the selected block and compared with its expected value (step S16). Then, a diagonal pattern is written into the selected block (step S18). For example, “0” data is written into a memory cell of the first bit from the left end in the block at the block address N=0, and “0” data is written into a memory cell of the second bit from the left end in a block at a block address N=1. As described above, a different pattern is written in each block.
Next, whether the block address N at that point in time is a last block address is determined (step S20). When it is not the last block address (step S20: No), one is added to the block address N (step S22), and the aforementioned steps from step S14 are repeated.
On the other hand, when the block address N at that point in time is the last block address (step S20: Yes), the block address N is reset again to “0” (step S30) as shown in FIG. 20.
Then, the written data is read from the memory cells in the block at the block address N (step S32). The read data is then compared with its expected value (step S34). For example, it is determined whether the read data is “011111 . . . ” when the block address N is “0” and whether the read data is “101111 . . . ” when the block address N is “1”.
Thereafter, whether the block address N at that point in time is the last block address is determined (step S36). When it is not the last block address (step S36: No), one is added to the block address N (step S38), and the aforementioned steps from step S32 are repeated.
On the other hand, when the block address N at that point in time is the last block address (step S36: Yes), this test process is completed.
A defective block found by the aforementioned test process needs not to be used in an actual operation. Namely, a row decoder circuit has a disable function which, even when a request for access to a defective block is received, allows the block address found in the test not to be selected. FIG. 21 shows a row decoder having the aforementioned disable function.
The row decoder shown in FIG. 21 includes a laser weld fuse FS, and by blowing this fuse FS, the corresponding defective block is not accessed.
Moreover, recently, a ROM fuse type row decoder such as shown in FIG. 22 is also realized to reduce costs and facilitate data conversion. In the row decoder shown in FIG. 22, by temporarily driving a fuse set signal FUSESET of a defective block high and fixing a node N10 of a latch circuit LT10 low, the same situation as when a fuse is blown is created. Namely, by fixing the node N10 of the latch circuit 10 low, a transistor Tr10 is turned off, and consequently, this block address can not be accessed. In other words, the latch circuit LT10 functions as a ROM which stores a defective block in a nonvolatile manner. Such a ROM fuse type row decoder is disclosed, for example, in Japanese Patent Laid-open No. 2002-117692 and its corresponding published U.S. patent application No. 2002/0039311. The entire contents of Japanese Patent Laid-open No. 2002-117692 and the published U.S. patent application No. 2002/0039311 are incorporated herein by reference.
In the aforementioned test, however, it is necessary that memory cells of each block are actually accessed, and that an erase operation, a write operation, and a read operation are performed in all blocks. Hence, there arises a problem that the test process needs a lot of time. In particular, with an increase in the capacity of a semiconductor memory device, the number of blocks increases, which causes a problem that the process of testing whether a one-to-one correspondence is established between blocks and addresses forms a significantly increased proportion of the entire test process.